This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-278460, filed on Sep. 13, 2001, the entire content of which is incorporated herein by reference.
The present invention relates generally to voltage generating circuitry adaptable for use in semiconductor integrated circuit devices and, more particularly, to a constant voltage generation circuit capable of generating a high output voltage even upon occurrence of a potential decrease in power supply voltage.
FIG. 9A is a diagram showing one typical prior known constant voltage generation circuit. This constant voltage generation circuit 1 is equipped with a constant current generator circuit 10 of the so-called Wilson type which functions to output a constant-level voltage and a switching circuit 20 operable to switch between its active state and inactive state.
The Wilson type constant current generator circuit 10 is generally configured from a p-channel metal oxide semiconductor (pMOS) transistor p1 of the enhancement type (E-type) which has a standard threshold voltage (Vtp) with a negative value, an E-type pMOS transistor p2 which is the same in size as the transistor p1, an E-type n-channel MOS (nMOS) transistor n1 having a low threshold voltage Vtn1, and an E-type nMOS transistor n2 having its threshold voltage Vtn2 higher than this Vtn1 value.
The transistor p1 is diode-connectedxe2x80x94that is, its drain and gate are connected together. The language xe2x80x9cdiode-connectedxe2x80x9d will be used hereinafter in the same technical meaning. The transistors p1 and p2 have gates coupled together, thereby making up a current mirror circuit. The nMOS transistor n1 and a resistor 11 are connected between the drain of this transistor p1 and ground voltage Vss, thus forming a first current flow path 12. This resistor 11 has a resistance value R1, which is larger than the turn-on resistance of the nMOS transistor n1.
The nMOS transistor n2 and a switching transistor 24 of a switching circuit 20 as will be later described are connected between the drain of transistor p2 and ground voltage Vss to thereby form a second current flow path 13. The transistor n1""s gate is connected to the gate and drain of the transistor n2. A potential NBIAS at the drain of this transistor n2 is for use as an output voltage Vo of the constant voltage generation circuit 1.
The switching circuit 20 is constituted from a switching pMOS transistor 21, a switching nMOS transistor 22, an inverter 23, and a switching nMOS transistor 24. The pMOS transistor 21 is connected between the source of pMOS transistor p1 and a power supply voltage Vcc. In responding to receipt of an enable signal ENB such as shown in FIG. 9B, the transistor 21 performs a switching operation to go from its turn-on state to turn-off state, whereby the first current flow path 12 made up of the pMOS transistor p1 and nMOS transistor n1 turns on. Note here that although a pMOS transistor 25 which has the same characteristics as the switching pMOS transistor 21 is connected on the pMOS transistor p2 side also, this is merely for the purpose of equalizing potential levels at the sources of the both transistors p1, p2. Transistor 25 is coupled to ground at its gate. Thus, transistor 25 is always kept conductivexe2x80x94i.e. turns on in any events.
The nMOS transistor 24 is disposed between the source of nMOS transistor n2 and ground voltage Vss and is designed to switch from its turn-off to turn-on state in response to receipt of the enable signal ENB. Whereby, the second current flow path 13 made up of the pMOS transistor p2 and nMOS transistor n2 turns on. The switching nMOS transistor 22 is the one that is operatively responsive to receipt of the enable signal ENB for performing reset and set-up of a connection node O1.
An operation of the circuitry of FIG. 9A is as follows. Upon receiving of the enable signal ENB, the switching circuit 20 causes the Wilson constant current generator circuit 10 to switch from its inactive state to active state. Due to the current mirror connection of the transistors p1, p2, a current Ip2 which flows between the source and drain of pMOS transistor p2 becomes equal to a current Ip1 flowing between the source and drain of pMOS transistor p1. These currents Ip1, Ip2 flow into the nMOS transistors n1, n2, respectively, thereby becoming currents In1, In2. Thus, In1 and In2 also are equal to each other. As the resistance value R1 of resistor 11 is made larger than the turn-on resistance of nMOS transistor n1, the current versus voltage characteristics of the current flow path 12 is representable by straight line xe2x80x9cAxe2x80x9d (with a gradient of 1/R1) shown in a graph of FIG. 9C, wherein line A crosses the lateral axis of this graph at a value Vtn1. On the other hand, the current-voltage characteristics of the current flow path 13 may be represented by exponential curve xe2x80x9cBxe2x80x9d with intercept Vtn2 on the lateral axis. The output voltage Vo of the constant voltage generation circuit 1 is determinable by a cross point C (operating point) of the characteristic line A and curve B owing to the functionality of the current mirror connection of transistors p1, p2; thus, it becomes a constant voltage without any potential dependency on the power supply voltage Vccxe2x80x94say, Vcc-independent constant voltage. Additionally, curve D is plotted in FIG. 9C to indicate the transistor p1""s load curve whereas curve E indicates a drain current Ip2 of the transistor p2 and its load curve.
Unfortunately the constant voltage generation circuit shown in FIG. 9 is encountered with a problem which follows. In cases where the supply voltage Vcc potentially decreases or drops down in accordance with the scaling of on-chip circuit elements, it is difficult to guarantee provision of the output voltage required. More specifically, in the constant voltage generation circuit of FIG. 9, the minimum value Vccmin of the supply voltage Vcc for operation stability is determined by the first current flow path 12 and is given as follows:
Vccmin=Voxe2x88x92Vtn1+|Vtp|+dVds1,xe2x80x83xe2x80x83[Formula 1]
where dvds1 is the drain-source voltage of transistor p1.
As can be seen from Formula 1, the only approach to reducing Vccmin while maintaining the output voltage Vo at the required potential level is to lower the threshold voltage Vtp.
This approach, however, does not come without accompanying a problem as to an increase in production costs due to the necessity for xe2x80x9cspecialxe2x80x9d channel implantation processes. Consequently, the prior art circuitry suffers from a problem that Vccmin reduction is hardly achievable without lowering the output voltage Vo per se.
The present invention may provide a constant voltage generating circuit in accordance with a first aspect thereof, which comprises a first constant current generation circuit which includes a first transistor and a second transistor and generates a first voltage and a first current as determined depending on a difference in threshold voltage between the first and second transistors, a second constant current generation circuit configured to generate a second current that is proportional to the first current, and a voltage generation circuit which includes a third transistor having its gate and drain connected together and which generates a second voltage when the second current flows in the third transistor.
The present invention may provide a constant voltage generating circuit in accordance with a second aspect thereof, which comprises a first constant current generation circuit which includes a first transistor and a second transistor and generates a first voltage and a first current as determined depending on a difference in transconduntance between the first and second transistors, a second constant current generation circuit configured to generate a second current that is proportional to the first current, and a voltage generation circuit which includes a third transistor having its gate and drain connected together and which generates a second voltage when the second current flows in the third transistor.
A constant voltage generating circuit in accordance with a third aspect of this invention comprises a first current flow path, a second current flow path and a third current flow path. The first current path includes a serial combination of a diode-coupled first metal insulator semiconductor (MIS) transistor of a first conductivity type, a second MIS transistor of a second conductivity type, and a first resistor. The second current path includes a serial combination of a third MIS transistor of the first conductivity type as current mirror-connected to the first MIS transistor and a diode-coupled fourth MIS transistor of the second conductivity type. The third current path includes a fifth MIS transistor of the first conductivity type as current mirror-connected to the first MIS transistor. The second and fourth MIS transistors have their gates connected together. The third current path is operatively associated with a constant voltage output unit as connected thereto. This unit includes a diode-coupled sixth MIS transistor that is higher in threshold voltage than the fourth MIS transistor.
In accordance with a fourth aspect of the present invention, a constant voltage generating circuit comprises first to third current flow paths. The first current path includes a serial combination of a diode-coupled first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, and a first resistor. The second current path includes a serial combination of a third MIS transistor of the first conductivity type which is current mirror-connected to the first MIS transistor and a diode-coupled fourth MIS transistor of the second conductivity type. The third current path includes a fifth MIS transistor of the first conductivity type as current mirror-connected to the first MIS transistor. The second and fourth MIS transistors have their gates connected together. The third current path is associated with a constant voltage output unit as connected thereto. This unit is made up of a connection of a diode-coupled sixth MIS transistor and a second resistor. The second resistor has a resistance value greater than the turn-on resistance value of the sixth MIS transistor.
In accordance with a fifth aspect of the invention, a constant voltage generating circuit comprises first to third current flow paths. The first current path includes a serial combination of a diode-coupled first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, and a first resistor. The second current path includes a serial combination of a third MIS transistor of the first conductivity type as current mirror-connected to the first MIS transistor and a diode-coupled fourth MIS transistor of the second conductivity type. The third current path includes a fifth MIS transistor of the first conductivity type as current mirror-connected to the first MIS transistor. The second MIS transistor and the fourth MIS transistor have their gates connected together. The third path is operatively associated with a constant voltage output unit as connected thereto. This unit includes a diode-coupled sixth MIS transistor lower in transconductance than the fourth MIS transistor.
In accordance with a sixth aspect of the invention, a constant voltage generating circuit comprises first to third current flow paths. The first current path includes a serial combination of a diode-coupled first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, and a first resistor. The second current path includes a serial combination of a third MIS transistor of the first conductivity type as current mirror-connected to the first MIS transistor and a diode-coupled fourth MIS transistor of the second conductivity type. The third current path includes a fifth MIS transistor of the first conductivity type as current mirror-connected to the first MIS transistor. The second and fourth MIS transistors have their gates connected together. A constant voltage output unit is connected to the third current path. This constant voltage output unit includes a diode-coupled sixth MIS transistor. A third current flowing in the third current path is greater in magnitude than a second current flowing in the second current path.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.